Field of the Invention
The present invention relates to a semiconductor device and particularly relates to a semiconductor device provided with a clock adjustment circuit for controlling the phase of an internal clock signal.
Description of Related Art
A semiconductor device such as a DRAM (Dynamic Random Access Memory) is provided with a clock adjustment circuit such as a DLL (Delay Locked Loop) circuit. For example, a semiconductor device is provided with a DLL circuit which intermittently carries out a phase adjustment operation (Japanese Patent Application Laid Open No. 2011-109524).